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28 lines
650 B
Plaintext
28 lines
650 B
Plaintext
SHORT L1 data TLB miss rate/ratio
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EVENTSET
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PMC0 INST_RETIRED
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PMC1 CPU_CYCLES
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PMC2 L1D_TLB_REFILL_RD
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PMC3 L1D_TLB_REFILL_WR
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METRICS
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Runtime (RDTSC) [s] time
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Clock [MHz] 1.E-06*PMC1/time
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CPI PMC1/PMC0
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L1 DTLB load misses PMC2
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L1 DTLB load miss rate PMC2/PMC0
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L1 DTLB store misses PMC3
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L1 DTLB store miss rate PMC3/PMC0
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LONG
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Formulas:
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L1 DTLB load misses = L1D_TLB_REFILL_RD
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L1 DTLB load miss rate = L1D_TLB_REFILL_RD / INST_RETIRED
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L1 DTLB store misses = L1D_TLB_REFILL_WR
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L1 DTLB store miss rate = L1D_TLB_REFILL_WR / INST_RETIRED
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-
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The DTLB load and store miss rates gives a measure how often a TLB miss occurred
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per instruction.
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