SHORT  L1 data TLB miss rate/ratio

EVENTSET
PMC0  INST_RETIRED
PMC1  CPU_CYCLES
PMC2  L1D_TLB_REFILL_RD
PMC3  L1D_TLB_REFILL_WR

METRICS
Runtime (RDTSC) [s] time
Clock [MHz] 1.E-06*PMC1/time
CPI  PMC1/PMC0
L1 DTLB load misses     PMC2
L1 DTLB load miss rate  PMC2/PMC0
L1 DTLB store misses     PMC3
L1 DTLB store miss rate  PMC3/PMC0

LONG
Formulas:
L1 DTLB load misses = L1D_TLB_REFILL_RD
L1 DTLB load miss rate = L1D_TLB_REFILL_RD / INST_RETIRED
L1 DTLB store misses = L1D_TLB_REFILL_WR
L1 DTLB store miss rate = L1D_TLB_REFILL_WR / INST_RETIRED
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The DTLB load and store miss rates gives a measure how often a TLB miss occurred
per instruction.