104 lines
4.6 KiB
C
104 lines
4.6 KiB
C
/*
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* Copyright (C) 2022 NHR@FAU, University Erlangen-Nuremberg.
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* All rights reserved. This file is part of MD-Bench.
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* Use of this source code is governed by a LGPL-3.0
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* license that can be found in the LICENSE file.
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*/
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#include <stdlib.h>
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#include <string.h>
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#include <immintrin.h>
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#ifndef NO_ZMM_INTRIN
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# include <zmmintrin.h>
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#endif
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#define MD_SIMD_FLOAT __m512
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#define MD_SIMD_MASK __mmask16
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#define MD_SIMD_INT __m256i
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#define MD_SIMD_IBOOL __mmask16
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#define MD_SIMD_INT32 __m512i
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#define MD_SIMD_BITMASK MD_SIMD_INT32
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static inline MD_SIMD_BITMASK simd_load_bitmask(const int *m) {
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return _mm512_load_si512(m);
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}
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static inline MD_SIMD_INT32 simd_int32_broadcast(int a) {
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return _mm512_set1_epi32(a);
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}
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static inline MD_SIMD_IBOOL simd_test_bits(MD_SIMD_FLOAT a) {
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return _mm512_test_epi32_mask(_mm512_castps_si512(a), _mm512_castps_si512(a));
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}
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static inline MD_SIMD_MASK cvtIB2B(MD_SIMD_IBOOL a) { return a; }
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static inline MD_SIMD_FLOAT simd_broadcast(float scalar) { return _mm512_set1_ps(scalar); }
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static inline MD_SIMD_FLOAT simd_zero() { return _mm512_set1_ps(0.0f); }
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static inline MD_SIMD_FLOAT simd_add(MD_SIMD_FLOAT a, MD_SIMD_FLOAT b) { return _mm512_add_ps(a, b); }
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static inline MD_SIMD_FLOAT simd_sub(MD_SIMD_FLOAT a, MD_SIMD_FLOAT b) { return _mm512_sub_ps(a, b); }
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static inline MD_SIMD_FLOAT simd_mul(MD_SIMD_FLOAT a, MD_SIMD_FLOAT b) { return _mm512_mul_ps(a, b); }
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static inline MD_SIMD_FLOAT simd_fma(MD_SIMD_FLOAT a, MD_SIMD_FLOAT b, MD_SIMD_FLOAT c) { return _mm512_fmadd_ps(a, b, c); }
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static inline MD_SIMD_FLOAT simd_reciprocal(MD_SIMD_FLOAT a) { return _mm512_rcp14_ps(a); }
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static inline MD_SIMD_FLOAT simd_masked_add(MD_SIMD_FLOAT a, MD_SIMD_FLOAT b, MD_SIMD_MASK m) { return _mm512_mask_add_ps(a, m, a, b); }
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static inline MD_SIMD_MASK simd_mask_and(MD_SIMD_MASK a, MD_SIMD_MASK b) { return _kand_mask16(a, b); }
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static inline MD_SIMD_MASK simd_mask_cond_lt(MD_SIMD_FLOAT a, MD_SIMD_FLOAT b) { return _mm512_cmp_ps_mask(a, b, _CMP_LT_OQ); }
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static inline MD_SIMD_MASK simd_mask_from_u32(unsigned int a) { return _cvtu32_mask16(a); }
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static inline unsigned int simd_mask_to_u32(MD_SIMD_MASK a) { return _cvtmask16_u32(a); }
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static inline MD_SIMD_FLOAT simd_load(MD_FLOAT *p) { return _mm512_load_ps(p); }
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static inline void simd_store(MD_FLOAT *p, MD_SIMD_FLOAT a) { _mm512_store_ps(p, a); }
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static inline MD_SIMD_FLOAT select_by_mask(MD_SIMD_FLOAT a, MD_SIMD_MASK m) { return _mm512_mask_mov_ps(_mm512_setzero_ps(), m, a); }
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static inline MD_FLOAT simd_h_reduce_sum(MD_SIMD_FLOAT a) {
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// This would only be called in a Mx16 configuration, which is not valid in GROMACS
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fprintf(stderr, "simd_h_reduce_sum(): Called with AVX512 intrinsics and single-precision which is not valid!\n");
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exit(-1);
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return 0.0;
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}
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static inline MD_FLOAT simd_incr_reduced_sum(MD_FLOAT *m, MD_SIMD_FLOAT v0, MD_SIMD_FLOAT v1, MD_SIMD_FLOAT v2, MD_SIMD_FLOAT v3) {
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// This would only be called in a Mx16 configuration, which is not valid in GROMACS
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fprintf(stderr, "simd_h_reduce_sum(): Called with AVX512 intrinsics and single-precision which is not valid!\n");
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exit(-1);
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return 0.0;
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}
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static inline MD_SIMD_FLOAT simd_load_h_duplicate(const float* m) {
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return _mm512_castpd_ps(_mm512_broadcast_f64x4(_mm256_load_pd((const double *)(m))));
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}
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static inline MD_SIMD_FLOAT simd_load_h_dual(const float* m) {
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return _mm512_shuffle_f32x4(_mm512_broadcastss_ps(_mm_load_ss(m)), _mm512_broadcastss_ps(_mm_load_ss(m + 1)), 0x44);
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}
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static inline MD_FLOAT simd_h_dual_incr_reduced_sum(float* m, MD_SIMD_FLOAT v0, MD_SIMD_FLOAT v1) {
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__m512 t0, t1;
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__m128 t2, t3;
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t0 = _mm512_shuffle_f32x4(v0, v1, 0x88);
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t1 = _mm512_shuffle_f32x4(v0, v1, 0xdd);
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t0 = _mm512_add_ps(t0, t1);
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t0 = _mm512_add_ps(t0, _mm512_permute_ps(t0, 0x4e));
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t0 = _mm512_add_ps(t0, _mm512_permute_ps(t0, 0xb1));
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t0 = _mm512_maskz_compress_ps(simd_mask_from_u32(0x1111ul), t0);
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t3 = _mm512_castps512_ps128(t0);
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t2 = _mm_load_ps(m);
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t2 = _mm_add_ps(t2, t3);
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_mm_store_ps(m, t2);
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t3 = _mm_add_ps(t3, _mm_permute_ps(t3, 0x4e));
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t3 = _mm_add_ps(t3, _mm_permute_ps(t3, 0xb1));
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return _mm_cvtss_f32(t3);
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}
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static inline void simd_h_decr(MD_FLOAT *m, MD_SIMD_FLOAT a) {
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__m256 t;
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a = _mm512_add_ps(a, _mm512_shuffle_f32x4(a, a, 0xee));
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t = _mm256_load_ps(m);
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t = _mm256_sub_ps(t, _mm512_castps512_ps256(a));
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_mm256_store_ps(m, t);
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}
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static inline void simd_h_decr3(MD_FLOAT *m, MD_SIMD_FLOAT a0, MD_SIMD_FLOAT a1, MD_SIMD_FLOAT a2) {
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simd_h_decr(m, a0);
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simd_h_decr(m + CLUSTER_N, a1);
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simd_h_decr(m + CLUSTER_N * 2, a2);
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}
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