From 0bb7e3c61ff40a6771e659e7e1c7d0c08d940a6d Mon Sep 17 00:00:00 2001 From: Rafael Ravedutti Date: Thu, 17 Jun 2021 03:07:34 +0200 Subject: [PATCH] Add cache simulator script and first results Signed-off-by: Rafael Ravedutti --- util/cache.py | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 util/cache.py diff --git a/util/cache.py b/util/cache.py new file mode 100644 index 0000000..2d31e33 --- /dev/null +++ b/util/cache.py @@ -0,0 +1,33 @@ +import sys +from cachesim import CacheSimulator, Cache, MainMemory + +filename = sys.argv[1] +mem = MainMemory() + +#l3 = Cache("L3", 20480, 16, 64, "LRU") # 20MB: 20480 sets, 16-ways with cacheline size of 64 bytes +#l2 = Cache("L2", 256, 4, 64, "LRU", store_to=l3, load_from=l3) # 256KB +#l1 = Cache("L1", 64, 8, 64, "LRU", store_to=l2, load_from=l2) # 32KB + +# Cascade Lake +l3 = Cache("L3", 28672, 11, 64, "LRU") # 28MB: 11-ways with cacheline size of 64 bytes +l2 = Cache("L2", 1024, 16, 64, "LRU", store_to=l3, load_from=l3) # 1MB +l1 = Cache("L1", 32, 8, 64, "LRU", store_to=l2, load_from=l2) # 32KB +mem.load_to(l3) +mem.store_from(l3) +cs = CacheSimulator(l1, mem) + +with open(filename, 'r') as fp: + for line in fp.readlines(): + op, addr = line.split(": ") + op = op[0] + addr = int(addr, 16) + + if op == 'W': + cs.store(addr, length=8) + elif op == 'R': + cs.load(addr, length=8) + else: + sys.exit("Invalid operation: {}".format(op)) + +cs.force_write_back() +cs.print_stats()