80 lines
7.1 KiB
Plaintext
80 lines
7.1 KiB
Plaintext
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Intel(R) Architecture Code Analyzer Version - v3.0-28-g1ba2cbb build date: 2017-10-23;16:42:45
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Analyzed File - gromacs-avx512-sp.o
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Binary Format - 64Bit
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Architecture - SKX
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Analysis Type - Throughput
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Throughput Analysis Report
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--------------------------
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Block Throughput: 25.21 Cycles Throughput Bottleneck: Backend
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Loop Count: 22
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Port Binding In Cycles Per Iteration:
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--------------------------------------------------------------------------------------------------
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| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
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--------------------------------------------------------------------------------------------------
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| Cycles | 21.0 0.0 | 2.0 | 2.0 2.0 | 2.0 2.0 | 0.0 | 21.0 | 2.0 | 0.0 |
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--------------------------------------------------------------------------------------------------
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DV - Divider pipe (on port 0)
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D - Data fetch pipe (on ports 2 and 3)
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F - Macro Fusion with the previous instruction occurred
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* - instruction micro-ops not bound to a port
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^ - Micro Fusion occurred
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# - ESP Tracking sync uop was issued
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@ - SSE instruction followed an AVX256/AVX512 instruction, dozens of cycles penalty is expected
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X - instruction not supported, was not accounted in Analysis
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| Num Of | Ports pressure in cycles | |
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| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
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-----------------------------------------------------------------------------------------
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| 1 | | | 1.0 1.0 | | | | | | movsxd rdi, dword ptr [rsi+rdx*4]
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| 1 | | 1.0 | | | | | | | lea rdi, ptr [rdi+rdi*2]
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| 1 | | | | | | | 1.0 | | shl rdi, 0x5
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| 1 | | | | 1.0 1.0 | | | | | vmovupd zmm16, zmmword ptr [rcx+rdi*1]
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| 2 | | | 1.0 1.0 | | | 1.0 | | | vinsertf64x4 zmm17, zmm16, ymmword ptr [rcx+rdi*1], 0x1
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| 1 | | | | 1.0 1.0 | | | | | vbroadcastf64x4 zmm18, ymmword ptr [rcx+rdi*1+0x40]
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| 1 | | | | | | 1.0 | | | vshuff64x2 zmm16, zmm16, zmm16, 0xee
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| 1 | 1.0 | | | | | | | | vsubps zmm19, zmm6, zmm17
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| 1 | 1.0 | | | | | | | | vsubps zmm20, zmm10, zmm16
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| 1 | | | | | | 1.0 | | | vsubps zmm21, zmm12, zmm18
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| 1 | 1.0 | | | | | | | | vsubps zmm17, zmm9, zmm17
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| 1 | | | | | | 1.0 | | | vsubps zmm18, zmm14, zmm18
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| 1 | 1.0 | | | | | | | | vsubps zmm16, zmm11, zmm16
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| 1 | | | | | | 1.0 | | | vmulps zmm22, zmm21, zmm21
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| 1 | 1.0 | | | | | | | | vfmadd231ps zmm22, zmm20, zmm20
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| 1 | | | | | | 1.0 | | | vfmadd231ps zmm22, zmm19, zmm19
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| 1 | 1.0 | | | | | | | | vmulps zmm23, zmm18, zmm18
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| 1 | | | | | | 1.0 | | | vfmadd231ps zmm23, zmm16, zmm16
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| 1 | 1.0 | | | | | | | | vfmadd231ps zmm23, zmm17, zmm17
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| 3 | 2.0 | | | | | 1.0 | | | vrcp14ps zmm24, zmm22
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| 3 | 2.0 | | | | | 1.0 | | | vrcp14ps zmm25, zmm23
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| 1 | | | | | | 1.0 | | | vcmpps k2, zmm22, zmm0, 0x1
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| 1 | | | | | | 1.0 | | | vcmpps k1, zmm23, zmm0, 0x1
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| 1 | | | | | | 1.0 | | | vmulps zmm22, zmm24, zmm29
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| 1 | 1.0 | | | | | | | | vmulps zmm23, zmm24, zmm24
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| 1 | | | | | | 1.0 | | | vmulps zmm26, zmm25, zmm29
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| 1 | 1.0 | | | | | | | | vmulps zmm22, zmm23, zmm22
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| 1 | | | | | | 1.0 | | | vmulps zmm23, zmm25, zmm25
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| 1 | 1.0 | | | | | | | | vmulps zmm23, zmm23, zmm26
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| 1 | | | | | | 1.0 | | | vaddps zmm26, zmm22, zmm2
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| 1 | 1.0 | | | | | | | | vmulps zmm24, zmm1, zmm24
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| 1 | | | | | | 1.0 | | | vmulps zmm22, zmm24, zmm22
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| 1 | 1.0 | | | | | | | | vmulps zmm22, zmm22, zmm26
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| 1 | | | | | | 1.0 | | | vaddps zmm24, zmm23, zmm2
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| 1 | 1.0 | | | | | | | | vmulps zmm25, zmm1, zmm25
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| 1 | | | | | | 1.0 | | | vmulps zmm23, zmm25, zmm23
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| 1 | 1.0 | | | | | | | | vmulps zmm23, zmm23, zmm24
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| 1 | | | | | | 1.0 | | | vfmadd231ps zmm13{k2}, zmm22, zmm19
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| 1 | 1.0 | | | | | | | | vfmadd231ps zmm8{k2}, zmm22, zmm20
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| 1 | | | | | | 1.0 | | | vfmadd231ps zmm5{k2}, zmm22, zmm21
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| 1 | 1.0 | | | | | | | | vfmadd231ps zmm15{k1}, zmm23, zmm17
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| 1 | | | | | | 1.0 | | | vfmadd231ps zmm7{k1}, zmm23, zmm16
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| 1 | 1.0 | | | | | | | | vfmadd231ps zmm4{k1}, zmm23, zmm18
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| 1 | | 1.0 | | | | | | | inc rdx
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| 1* | | | | | | | | | cmp r12, rdx
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| 0*F | | | | | | | | | jnz 0xfffffffffffffef6
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| 1 | | | | | | | 1.0 | | jmp 0xfffffffffffffb58
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Total Num Of Uops: 51
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Analysis Notes:
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Backend allocation was stalled due to unavailable allocation resources.
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