2022-03-09 02:25:39 +01:00
|
|
|
ifeq ($(strip $(ISA)), SSE)
|
2022-11-15 00:55:46 +01:00
|
|
|
__ISA_SSE__=true
|
|
|
|
__SIMD_WIDTH_DBL__=2
|
2022-03-09 02:25:39 +01:00
|
|
|
else ifeq ($(strip $(ISA)), AVX)
|
2022-11-15 00:55:46 +01:00
|
|
|
__ISA_AVX__=true
|
|
|
|
__SIMD_WIDTH_DBL__=4
|
2022-11-15 01:24:30 +01:00
|
|
|
else ifeq ($(strip $(ISA)), AVX_FMA)
|
|
|
|
__ISA_AVX__=true
|
|
|
|
__ISA_AVX_FMA__=true
|
|
|
|
__SIMD_WIDTH_DBL__=4
|
2022-03-09 02:25:39 +01:00
|
|
|
else ifeq ($(strip $(ISA)), AVX2)
|
2022-11-15 00:55:46 +01:00
|
|
|
__ISA_AVX2__=true
|
|
|
|
#__SIMD_KERNEL__=true
|
|
|
|
__SIMD_WIDTH_DBL__=4
|
2022-03-09 02:25:39 +01:00
|
|
|
else ifeq ($(strip $(ISA)), AVX512)
|
2022-11-15 00:55:46 +01:00
|
|
|
__ISA_AVX512__=true
|
|
|
|
__SIMD_KERNEL__=true
|
|
|
|
__SIMD_WIDTH_DBL__=8
|
2022-03-09 02:25:39 +01:00
|
|
|
endif
|
|
|
|
|
2022-11-15 00:55:46 +01:00
|
|
|
# SIMD width is specified in double-precision, hence it may
|
|
|
|
# need to be adjusted for single-precision
|
2022-03-09 02:25:39 +01:00
|
|
|
ifeq ($(strip $(DATA_TYPE)), SP)
|
2022-11-15 00:55:46 +01:00
|
|
|
VECTOR_WIDTH=$(shell echo $$(( $(__SIMD_WIDTH_DBL__) * 2 )))
|
2022-03-15 02:40:56 +01:00
|
|
|
else
|
2022-11-15 00:55:46 +01:00
|
|
|
VECTOR_WIDTH=$(__SIMD_WIDTH_DBL__)
|
2022-03-09 02:25:39 +01:00
|
|
|
endif
|