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41 lines
1.4 KiB
Plaintext
41 lines
1.4 KiB
Plaintext
SHORT L2 cache miss rate/ratio
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EVENTSET
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PMC0 PM_L2_ST_MISS
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PMC1 PM_L2_LD_MISS
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PMC2 PM_L2_LD_DISP
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PMC3 PM_L2_ST_DISP
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PMC4 PM_RUN_INST_CMPL
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PMC5 PM_RUN_CYC
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METRICS
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Runtime (RDTSC) [s] time
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CPI PMC5/PMC4
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L2 request rate = (PMC2+PMC3)/PMC4
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L2 miss rate = (PMC0+PMC1)/PMC4
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L2 miss ratio = (PMC0+PMC1)/(PMC2+PMC3)
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LONG
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Formulas:
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L2 request rate = (PM_L2_LD_DISP+PM_L2_ST_DISP)/PM_RUN_INST_CMPL
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L2 miss rate = (PM_L2_LD_MISS+PM_L2_ST_MISS)/PM_RUN_INST_CMPL
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L2 miss ratio = (PM_L2_LD_MISS+PM_L2_ST_MISS)/(PM_L2_LD_DISP+PM_L2_ST_DISP)
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L2 load request rate = PM_L2_LD_DISP/PM_RUN_INST_CMPL
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L2 store request rate = PM_L2_ST_DISP/PM_RUN_INST_CMPL
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L2 load miss rate = PM_L2_LD_MISS/PM_RUN_INST_CMPL
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L2 store miss rate = PM_L2_ST_DISP/PM_RUN_INST_CMPL
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L2 load miss ratio = PM_L2_LD_MISS/(PM_L2_LD_DISP+PM_L2_ST_DISP)
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L2 store miss ratio = PM_L2_ST_MISS/(PM_L2_LD_DISP+PM_L2_ST_DISP)
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-
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This group measures the locality of your data accesses with regard to the
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L2 Cache. L2 request rate tells you how data intensive your code is
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or how many Data accesses you have in average per instruction.
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The L2 miss rate gives a measure how often it was necessary to get
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cachelines from memory. And finally L2 miss ratio tells you how many of your
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memory references required a cacheline to be loaded from a higher level.
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While the Data cache miss rate might be given by your algorithm you should
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try to get Data cache miss ratio as low as possible by increasing your cache reuse.
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