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24 lines
719 B
Plaintext
24 lines
719 B
Plaintext
SHORT TLB Misses
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EVENTSET
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PMC0 LONG_DATA_PAGE_WALK
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PMC1 DATA_PAGE_WALK
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METRICS
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Runtime (RDTSC) [s] time
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L1 TLB misses [misses/s] PMC1/time
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L2 TLB misses [misses/s] PMC0/time
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L1 TLB misses per L2 TLB miss PMC1/PMC0
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LONG
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Formulas:
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L1 TLB misses [misses/s] = DATA_PAGE_WALK/time
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L2 TLB misses [misses/s] = LONG_DATA_PAGE_WALK/time
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L1 TLB misses per L2 TLB miss = DATA_PAGE_WALK/LONG_DATA_PAGE_WALK
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-
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Analysis of the layered TLB of the Intel Xeon Phi. According to the book
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'Intel Xeon Phi Coprocessor High-Performance Programming' by James Jeffers and
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James Reinders, a high L1 TLB misses per L2 TLB miss ratio suggests that your
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working set fits into the L2 TLB but not in L1 TLB. Using large pages may be
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beneficial.
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