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46 lines
1.9 KiB
Plaintext
46 lines
1.9 KiB
Plaintext
SHORT Cycle Activities (Stalls)
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EVENTSET
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FIXC0 INSTR_RETIRED_ANY
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FIXC1 CPU_CLK_UNHALTED_CORE
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FIXC2 CPU_CLK_UNHALTED_REF
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PMC0 CYCLE_ACTIVITY_STALLS_L2_PENDING
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PMC1 CYCLE_ACTIVITY_STALLS_LDM_PENDING
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PMC2 CYCLE_ACTIVITY_STALLS_L1D_PENDING
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PMC3 CYCLE_ACTIVITY_STALLS_TOTAL
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METRICS
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Runtime (RDTSC) [s] time
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Runtime unhalted [s] FIXC1*inverseClock
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Clock [MHz] 1.E-06*(FIXC1/FIXC2)/inverseClock
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CPI FIXC1/FIXC0
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Total execution stalls PMC3
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Stalls caused by L1D misses [%] (PMC2/PMC3)*100
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Stalls caused by L2 misses [%] (PMC0/PMC3)*100
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Stalls caused by memory loads [%] (PMC1/PMC3)*100
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Execution stall rate [%] (PMC3/FIXC1)*100
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Stalls caused by L1D misses rate [%] (PMC2/FIXC1)*100
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Stalls caused by L2 misses rate [%] (PMC0/FIXC1)*100
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Stalls caused by memory loads rate [%] (PMC1/FIXC1)*100
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LONG
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Formulas:
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Total execution stalls = CYCLE_ACTIVITY_STALLS_TOTAL
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Stalls caused by L1D misses [%] = (CYCLE_ACTIVITY_STALLS_L1D_PENDING/CYCLE_ACTIVITY_STALLS_TOTAL)*100
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Stalls caused by L2 misses [%] = (CYCLE_ACTIVITY_STALLS_L2_PENDING/CYCLE_ACTIVITY_STALLS_TOTAL)*100
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Stalls caused by memory loads [%] = (CYCLE_ACTIVITY_STALLS_LDM_PENDING/CYCLE_ACTIVITY_STALLS_TOTAL)*100
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Execution stall rate [%] = (CYCLE_ACTIVITY_STALLS_TOTAL/CPU_CLK_UNHALTED_CORE)*100
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Stalls caused by L1D misses rate [%] = (CYCLE_ACTIVITY_STALLS_L1D_PENDING/CPU_CLK_UNHALTED_CORE)*100
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Stalls caused by L2 misses rate [%] = (CYCLE_ACTIVITY_STALLS_L2_PENDING/CPU_CLK_UNHALTED_CORE)*100
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Stalls caused by memory loads rate [%] = (CYCLE_ACTIVITY_STALLS_LDM_PENDING/CPU_CLK_UNHALTED_CORE)*100
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--
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This performance group measures the stalls caused by data traffic in the cache
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hierarchy.
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CYCLE_ACTIVITY_STALLS_TOTAL: Total execution stalls.
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CYCLE_ACTIVITY_STALLS_L1D_PENDING: Execution stalls while L1 cache miss demand
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load is outstanding.
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CYCLE_ACTIVITY_STALLS_L2_PENDING: Execution stalls while L2 cache miss demand
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load is outstanding.
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CYCLE_ACTIVITY_STALLS_LDM_PENDING: Execution stalls while memory subsystem has
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an outstanding load.
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