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29 lines
758 B
Plaintext
29 lines
758 B
Plaintext
SHORT Single Precision MFLOP/s
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EVENTSET
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FIXC1 ACTUAL_CPU_CLOCK
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FIXC2 MAX_CPU_CLOCK
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PMC0 RETIRED_INSTRUCTIONS
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PMC1 CPU_CLOCKS_UNHALTED
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PMC2 RETIRED_SSE_AVX_FLOPS_ALL
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PMC3 MERGE
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METRICS
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Runtime (RDTSC) [s] time
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Runtime unhalted [s] FIXC1*inverseClock
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Clock [MHz] 1.E-06*(FIXC1/FIXC2)/inverseClock
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CPI PMC1/PMC0
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SP [MFLOP/s] 1.0E-06*(PMC2)/time
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LONG
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Formulas:
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CPI = CPU_CLOCKS_UNHALTED/RETIRED_INSTRUCTIONS
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SP [MFLOP/s] = 1.0E-06*(RETIRED_SSE_AVX_FLOPS_ALL)/time
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-
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Profiling group to measure (single-precisision) FLOP rate. The event might
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have a higher per-cycle increment than 15, so the MERGE event is required. In
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contrast to AMD Zen, the Zen2 microarchitecture does not provide events to
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differentiate between single- and double-precision.
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