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53 lines
2.0 KiB
Plaintext
53 lines
2.0 KiB
Plaintext
SHORT L3 cache miss rate/ratio
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EVENTSET
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FIXC0 INSTR_RETIRED_ANY
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FIXC1 CPU_CLK_UNHALTED_CORE
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FIXC2 CPU_CLK_UNHALTED_REF
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CBOX0C0 LLC_HITS_ALL
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CBOX0C1 LLC_MISSES_ALL
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CBOX1C0 LLC_HITS_ALL
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CBOX1C1 LLC_MISSES_ALL
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CBOX2C0 LLC_HITS_ALL
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CBOX2C1 LLC_MISSES_ALL
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CBOX3C0 LLC_HITS_ALL
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CBOX3C1 LLC_MISSES_ALL
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CBOX4C0 LLC_HITS_ALL
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CBOX4C1 LLC_MISSES_ALL
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CBOX5C0 LLC_HITS_ALL
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CBOX5C1 LLC_MISSES_ALL
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CBOX6C0 LLC_HITS_ALL
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CBOX6C1 LLC_MISSES_ALL
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CBOX7C0 LLC_HITS_ALL
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CBOX7C1 LLC_MISSES_ALL
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CBOX8C0 LLC_HITS_ALL
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CBOX8C1 LLC_MISSES_ALL
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CBOX9C0 LLC_HITS_ALL
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CBOX9C1 LLC_MISSES_ALL
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METRICS
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Runtime (RDTSC) [s] time
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Runtime unhalted [s] FIXC1*inverseClock
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Clock [MHz] 1.E-06*(FIXC1/FIXC2)/inverseClock
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CPI FIXC1/FIXC0
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L3 request rate (CBOX0C0+CBOX0C1+CBOX1C0+CBOX1C1+CBOX2C0+CBOX2C1+CBOX3C0+CBOX3C1+CBOX4C0+CBOX4C1+CBOX5C0+CBOX5C1+CBOX6C0+CBOX6C1+CBOX7C0+CBOX7C1+CBOX8C0+CBOX8C1+CBOX9C0+CBOX9C1)/FIXC0
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L3 miss rate (CBOX0C1+CBOX1C1+CBOX2C1+CBOX3C1+CBOX4C1+CBOX5C1+CBOX6C1+CBOX7C1+CBOX8C1+CBOX9C1)/FIXC0
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L3 miss ratio (CBOX0C1+CBOX1C1+CBOX2C1+CBOX3C1+CBOX4C1+CBOX5C1+CBOX6C1+CBOX7C1+CBOX8C1+CBOX9C1)/(CBOX0C0+CBOX0C1+CBOX1C0+CBOX1C1+CBOX2C0+CBOX2C1+CBOX3C0+CBOX3C1+CBOX4C0+CBOX4C1+CBOX5C0+CBOX5C1+CBOX6C0+CBOX6C1+CBOX7C0+CBOX7C1+CBOX8C0+CBOX8C1+CBOX9C0+CBOX9C1)
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LONG
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Formulas:
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L3 request rate = (SUM(LLC_HITS_ALL)+SUM(LLC_MISSES_ALL))/INSTR_RETIRED_ANY
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L3 miss rate = SUM(LLC_MISSES_ALL)/INSTR_RETIRED_ANY
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L3 miss ratio = SUM(LLC_MISSES_ALL)/(SUM(LLC_HITS_ALL)+SUM(LLC_MISSES_ALL))
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-
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This group measures the locality of your data accesses with regard to the
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L3 cache. L3 request rate tells you how data intensive your code is
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or how many data accesses you have on average per instruction.
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The L3 miss rate gives a measure how often it was necessary to get
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cache lines from memory. And finally L3 miss ratio tells you how many of your
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memory references required a cache line to be loaded from a higher level.
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While the data cache miss rate might be given by your algorithm you should
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try to get data cache miss ratio as low as possible by increasing your cache reuse.
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