cc-metric-collector/collectors/likwid/groups/skylakeX/TLB_DATA.txt
2021-03-25 14:47:10 +01:00

36 lines
1.2 KiB
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SHORT L2 data TLB miss rate/ratio
EVENTSET
FIXC0 INSTR_RETIRED_ANY
FIXC1 CPU_CLK_UNHALTED_CORE
FIXC2 CPU_CLK_UNHALTED_REF
PMC0 DTLB_LOAD_MISSES_CAUSES_A_WALK
PMC1 DTLB_STORE_MISSES_CAUSES_A_WALK
PMC2 DTLB_LOAD_MISSES_WALK_ACTIVE
PMC3 DTLB_STORE_MISSES_WALK_ACTIVE
METRICS
Runtime (RDTSC) [s] time
Runtime unhalted [s] FIXC1*inverseClock
Clock [MHz] 1.E-06*(FIXC1/FIXC2)/inverseClock
CPI FIXC1/FIXC0
L1 DTLB load misses PMC0
L1 DTLB load miss rate PMC0/FIXC0
L1 DTLB load miss duration [Cyc] PMC2/PMC0
L1 DTLB store misses PMC1
L1 DTLB store miss rate PMC1/FIXC0
L1 DTLB store miss duration [Cyc] PMC3/PMC1
LONG
Formulas:
L1 DTLB load misses = DTLB_LOAD_MISSES_CAUSES_A_WALK
L1 DTLB load miss rate = DTLB_LOAD_MISSES_CAUSES_A_WALK / INSTR_RETIRED_ANY
L1 DTLB load miss duration [Cyc] = DTLB_LOAD_MISSES_WALK_ACTIVE / DTLB_LOAD_MISSES_CAUSES_A_WALK
L1 DTLB store misses = DTLB_STORE_MISSES_CAUSES_A_WALK
L1 DTLB store miss rate = DTLB_STORE_MISSES_CAUSES_A_WALK / INSTR_RETIRED_ANY
L1 DTLB store miss duration [Cyc] = DTLB_STORE_MISSES_WALK_ACTIVE / DTLB_STORE_MISSES_CAUSES_A_WALK
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The DTLB load and store miss rates gives a measure how often a TLB miss occurred
per instruction. The duration measures the time in cycles how long a walk did take.