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34 lines
861 B
Plaintext
34 lines
861 B
Plaintext
SHORT Instruction cache miss rate/ratio
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EVENTSET
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FIXC0 INSTR_RETIRED_ANY
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FIXC1 CPU_CLK_UNHALTED_CORE
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FIXC2 CPU_CLK_UNHALTED_REF
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PMC0 ICACHE_ACCESSES
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PMC1 ICACHE_MISSES
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PMC2 ICACHE_IFETCH_STALL
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PMC3 ILD_STALL_IQ_FULL
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METRICS
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Runtime (RDTSC) [s] time
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Runtime unhalted [s] FIXC1*inverseClock
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Clock [MHz] 1.E-06*(FIXC1/FIXC2)/inverseClock
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CPI FIXC1/FIXC0
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L1I request rate PMC0/FIXC0
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L1I miss rate PMC1/FIXC0
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L1I miss ratio PMC1/PMC0
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L1I stalls PMC2
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L1I stall rate PMC2/FIXC0
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L1I queue full stalls PMC3
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L1I queue full stall rate PMC3/FIXC0
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LONG
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Formulas:
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L1I request rate = ICACHE_ACCESSES / INSTR_RETIRED_ANY
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L1I miss rate = ICACHE_MISSES / INSTR_RETIRED_ANY
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L1I miss ratio = ICACHE_MISSES / ICACHE_ACCESSES
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L1I stalls = ICACHE_IFETCH_STALL
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L1I stall rate = ICACHE_IFETCH_STALL / INSTR_RETIRED_ANY
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-
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This group measures some L1 instruction cache metrics.
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