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			33 lines
		
	
	
		
			1.2 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
	
	
			
		
		
	
	
			33 lines
		
	
	
		
			1.2 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
	
	
| SHORT Data cache miss rate/ratio
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| 
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| EVENTSET
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| PMC0  RETIRED_INSTRUCTIONS
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| PMC1  DATA_CACHE_ACCESSES
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| PMC2  DATA_CACHE_REFILLS_VALID
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| PMC3  DATA_CACHE_MISSES_ALL
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| 
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| METRICS
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| Runtime (RDTSC) [s] time
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| data cache misses PMC3
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| data cache request rate PMC1/PMC0
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| data cache miss rate (PMC2)/PMC0
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| data cache miss ratio (PMC2)/PMC1
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| 
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| LONG
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| Formulas:
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| data cache misses = DATA_CACHE_MISSES_ALL
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| data cache request rate = DATA_CACHE_ACCESSES / RETIRED_INSTRUCTIONS
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| data cache miss rate = (DATA_CACHE_REFILLS_VALID) / RETIRED_INSTRUCTIONS
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| data cache miss ratio = (DATA_CACHE_REFILLS_VALID)/DATA_CACHE_ACCESSES
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| -
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| This group measures the locality of your data accesses with regard to the
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| L1 cache. Data cache request rate tells you how data intensive your code is
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| or how many data accesses you have on average per instruction.
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| The data cache miss rate gives a measure how often it was necessary to get
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| cache lines from higher levels of the memory hierarchy. And finally
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| data cache miss ratio tells you how many of your memory references required
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| a cache line to be loaded from a higher level. While the# data cache miss rate
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| might be given by your algorithm you should try to get data cache miss ratio
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| as low as possible by increasing your cache reuse.
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| 
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