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39 lines
1.5 KiB
Plaintext
39 lines
1.5 KiB
Plaintext
SHORT Cycle Activities
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EVENTSET
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FIXC0 INSTR_RETIRED_ANY
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FIXC1 CPU_CLK_UNHALTED_CORE
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FIXC2 CPU_CLK_UNHALTED_REF
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PMC0 CYCLE_ACTIVITY_CYCLES_L2_PENDING
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PMC1 CYCLE_ACTIVITY_CYCLES_LDM_PENDING
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PMC2 CYCLE_ACTIVITY_CYCLES_L1D_PENDING
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PMC3 CYCLE_ACTIVITY_CYCLES_NO_EXECUTE
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METRICS
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Runtime (RDTSC) [s] time
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Runtime unhalted [s] FIXC1*inverseClock
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Clock [MHz] 1.E-06*(FIXC1/FIXC2)/inverseClock
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CPI FIXC1/FIXC0
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Cycles without execution [%] (PMC3/FIXC1)*100
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Cycles without execution due to L1D [%] (PMC2/FIXC1)*100
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Cycles without execution due to L2 [%] (PMC0/FIXC1)*100
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Cycles without execution due to memory loads [%] (PMC1/FIXC1)*100
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LONG
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Formulas:
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Cycles without execution [%] = CYCLE_ACTIVITY_CYCLES_NO_EXECUTE/CPU_CLK_UNHALTED_CORE*100
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Cycles with stalls due to L1D [%] = CYCLE_ACTIVITY_CYCLES_L1D_PENDING/CPU_CLK_UNHALTED_CORE*100
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Cycles with stalls due to L2 [%] = CYCLE_ACTIVITY_CYCLES_L2_PENDING/CPU_CLK_UNHALTED_CORE*100
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Cycles without execution due to memory loads [%] = CYCLE_ACTIVITY_CYCLES_LDM_PENDING/CPU_CLK_UNHALTED_CORE*100
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--
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This performance group measures the cycles while waiting for data from the cache
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and memory hierarchy.
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CYCLE_ACTIVITY_CYCLES_NO_EXECUTE: Counts number of cycles nothing is executed on
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any execution port.
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CYCLE_ACTIVITY_CYCLES_L1D_PENDING: Cycles while L1 cache miss demand load is
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outstanding.
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CYCLE_ACTIVITY_CYCLES_L2_PENDING: Cycles while L2 cache miss demand load is
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outstanding.
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CYCLE_ACTIVITY_CYCLES_LDM_PENDING: Cycles while memory subsystem has an
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outstanding load.
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