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49 lines
2.1 KiB
Plaintext
49 lines
2.1 KiB
Plaintext
SHORT L3 cache bandwidth in MBytes/s
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EVENTSET
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FIXC0 INSTR_RETIRED_ANY
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FIXC1 CPU_CLK_UNHALTED_CORE
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FIXC2 CPU_CLK_UNHALTED_REF
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PMC0 L2_LINES_IN_ALL
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PMC1 L2_TRANS_L2_WB
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PMC2 IDI_MISC_WB_DOWNGRADE
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PMC3 IDI_MISC_WB_UPGRADE
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METRICS
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Runtime (RDTSC) [s] time
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Runtime unhalted [s] FIXC1*inverseClock
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Clock [MHz] 1.E-06*(FIXC1/FIXC2)/inverseClock
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CPI FIXC1/FIXC0
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L3 load bandwidth [MBytes/s] 1.0E-06*PMC0*64.0/time
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L3 load data volume [GBytes] 1.0E-09*PMC0*64.0
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L3 evict bandwidth [MBytes/s] 1.0E-06*PMC3*64.0/time
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L3 evict data volume [GBytes] 1.0E-09*PMC3*64.0
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L3|MEM evict bandwidth [MBytes/s] 1.0E-06*PMC1*64.0/time
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L3|MEM evict data volume [GBytes] 1.0E-09*PMC1*64.0
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Dropped CLs bandwidth [MBytes/s] 1.0E-6*PMC2*64.0/time
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Dropped CLs data volume [GBytes] 1.0E-9*PMC2*64.0
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L3 bandwidth [MBytes/s] 1.0E-06*(PMC0+PMC1)*64.0/time
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L3 data volume [GBytes] 1.0E-09*(PMC0+PMC1)*64.0
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LONG
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Formulas:
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L3 load bandwidth [MBytes/s] = 1.0E-06*L2_LINES_IN_ALL*64.0/time
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L3 load data volume [GBytes] = 1.0E-09*L2_LINES_IN_ALL*64.0
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L3 evict bandwidth [MBytes/s] = 1.0E-06*IDI_MISC_WB_UPGRADE*64.0/time
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L3 evict data volume [GBytes] = 1.0E-09*IDI_MISC_WB_UPGRADE*64.0
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Dropped CLs bandwidth [MBytes/s] = 1.0E-6*IDI_MISC_WB_DOWNGRADE*64.0/time
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Dropped CLs data volume [GBytes] = 1.0E-9*IDI_MISC_WB_DOWNGRADE*64.0
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L3|MEM evict bandwidth [MBytes/s] = 1.0E-06*L2_TRANS_L2_WB*64.0/time
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L3|MEM evict data volume [GBytes] = 1.0E-09*L2_TRANS_L2_WB*64.0
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L3 bandwidth [MBytes/s] = 1.0E-06*(L2_LINES_IN_ALL+L2_TRANS_L2_WB)*64/time
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L3 data volume [GBytes] = 1.0E-09*(L2_LINES_IN_ALL+L2_TRANS_L2_WB)*64
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--
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Profiling group to measure L3 cache bandwidth and data volume. For Intel Skylake
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or Cascadelake, the L3 is a victim cache. This means that all data is loaded
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from memory directly into the L2 cache (if L3 prefetcher is inactive). Modified
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data in L2 is evicted to L3 (additional data transfer due to non-inclusivenss of
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L3 can be measured). Clean cache lines (only loaded data) might get dropped in
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L2 to reduce traffic. If amount of clean cache lines is smaller than L3, it
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might be evicted to L3 due to some heuristic.
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