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32 lines
1.1 KiB
Plaintext
32 lines
1.1 KiB
Plaintext
SHORT L2 cache miss rate/ratio
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EVENTSET
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PMC0 RETIRED_INSTRUCTIONS
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PMC1 REQUESTS_TO_L2_DC_FILL
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PMC2 L2_CACHE_MISS_DC_FILL
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METRICS
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Runtime (RDTSC) [s] time
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L2 request rate PMC1/PMC0
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L2 miss rate PMC2/PMC0
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L2 miss ratio PMC2/PMC1
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LONG
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Formulas:
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L2 request rate = L2_REQUESTS_ALL/INSTRUCTIONS_RETIRED
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L2 miss rate = L2_MISSES_ALL/INSTRUCTIONS_RETIRED
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L2 miss ratio = L2_MISSES_ALL/L2_REQUESTS_ALL
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-
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This group measures the locality of your data accesses with regard to the L2
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Cache. L2 request rate tells you how data intensive your code is or how many
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data accesses you have on average per instruction. The L2 miss rate gives a
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measure how often it was necessary to get cache lines from memory. And finally
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L2 miss ratio tells you how many of your memory references required a cache line
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to be loaded from a higher level. While the# data cache miss rate might be
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given by your algorithm you should try to get data cache miss ratio as low as
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possible by increasing your cache reuse. This group is inspired from the
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whitepaper -Basic Performance Measurements for AMD Athlon 64, AMD Opteron and
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AMD Phenom Processors- from Paul J. Drongowski.
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