SHORT L3 cache miss rate/ratio

EVENTSET
FIXC0  INSTR_RETIRED_ANY
FIXC1  CPU_CLK_UNHALTED_CORE
FIXC2  CPU_CLK_UNHALTED_REF
UPMC0  UNC_L3_HITS_ANY
UPMC1  UNC_L3_MISS_ANY

METRICS
Runtime (RDTSC) [s] time
Runtime unhalted [s] FIXC1*inverseClock
Clock [MHz]  1.E-06*(FIXC1/FIXC2)/inverseClock
CPI  FIXC1/FIXC0
L3 request rate   (UPMC0+UPMC1)/FIXC0
L3 miss rate   UPMC1/FIXC0
L3 miss ratio  UPMC1/(UPMC0+UPMC1)

LONG
Formulas:
L3 request rate = (UNC_L3_HITS_ANY+UNC_L3_MISS_ANY)/INSTR_RETIRED_ANY
L3 miss rate = UNC_L3_MISS_ANY/INSTR_RETIRED_ANY
L3 miss ratio = UNC_L3_MISS_ANY/(UNC_L3_HITS_ANY+UNC_L3_MISS_ANY)
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This group measures the locality of your data accesses with regard to the L3
Cache. L3 request rate tells you how data intensive your code is or how many
data accesses you have on average per instruction. The L3 miss rate gives a
measure how often it was necessary to get cache lines from memory. And finally
L3 miss ratio tells you how many of your memory references required a cache line
to be loaded from a higher level. While the data cache miss rate might be given
by your algorithm you should try to get data cache miss ratio as low as
possible by increasing your cache reuse.