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31 lines
905 B
Plaintext
31 lines
905 B
Plaintext
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SHORT TLB miss rate/ratio
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EVENTSET
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FIXC0 INSTR_RETIRED_ANY
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FIXC1 CPU_CLK_UNHALTED_CORE
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FIXC2 CPU_CLK_UNHALTED_REF
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PMC0 DTLB_MISSES_ANY
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PMC1 L1D_ALL_REF_ANY
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METRICS
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Runtime (RDTSC) [s] time
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Runtime unhalted [s] FIXC1*inverseClock
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Clock [MHz] 1.E-06*(FIXC1/FIXC2)/inverseClock
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CPI FIXC1/FIXC0
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L1 DTLB request rate PMC1/FIXC0
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L1 DTLB miss rate PMC0/FIXC0
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L1 DTLB miss ratio PMC0/PMC1
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LONG
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Formulas:
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L1 DTLB request rate = L1D_ALL_REF_ANY / INSTR_RETIRED_ANY
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DTLB miss rate = DTLB_MISSES_ANY / INSTR_RETIRED_ANY
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L1 DTLB miss ratio = DTLB_MISSES_ANY / L1D_ALL_REF_ANY
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-
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L1 DTLB request rate tells you how data intensive your code is
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or how many data accesses you have on average per instruction.
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The DTLB miss rate gives a measure how often a TLB miss occurred
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per instruction. And finally L1 DTLB miss ratio tells you how many
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of your memory references required caused a TLB miss on average.
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