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38 lines
1.5 KiB
Plaintext
38 lines
1.5 KiB
Plaintext
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SHORT L2 cache bandwidth in MBytes/s
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EVENTSET
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FIXC0 INSTR_RETIRED_ANY
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FIXC1 CPU_CLK_UNHALTED_CORE
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FIXC2 CPU_CLK_UNHALTED_REF
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PMC0 L1D_REPLACEMENT
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PMC1 L2_TRANS_L1D_WB
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PMC2 ICACHE_MISSES
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METRICS
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Runtime (RDTSC) [s] time
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Runtime unhalted [s] FIXC1*inverseClock
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Clock [MHz] 1.E-06*(FIXC1/FIXC2)/inverseClock
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CPI FIXC1/FIXC0
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L2D load bandwidth [MBytes/s] 1.0E-06*PMC0*64.0/time
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L2D load data volume [GBytes] 1.0E-09*PMC0*64.0
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L2D evict bandwidth [MBytes/s] 1.0E-06*PMC1*64.0/time
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L2D evict data volume [GBytes] 1.0E-09*PMC1*64.0
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L2 bandwidth [MBytes/s] 1.0E-06*(PMC0+PMC1+PMC2)*64.0/time
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L2 data volume [GBytes] 1.0E-09*(PMC0+PMC1+PMC2)*64.0
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LONG
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Formulas:
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L2D load bandwidth [MBytes/s] = 1.0E-06*L1D_REPLACEMENT*64.0/time
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L2D load data volume [GBytes] = 1.0E-09*L1D_REPLACEMENT*64.0
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L2D evict bandwidth [MBytes/s] = 1.0E-06*L2_TRANS_L1D_WB*64.0/time
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L2D evict data volume [GBytes] = 1.0E-09*L2_TRANS_L1D_WB*64.0
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L2 bandwidth [MBytes/s] = 1.0E-06*(L1D_REPLACEMENT+L2_TRANS_L1D_WB+ICACHE_MISSES)*64.0/time
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L2 data volume [GBytes] = 1.0E-09*(L1D_REPLACEMENT+L2_TRANS_L1D_WB+ICACHE_MISSES)*64.0
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-
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Profiling group to measure L2 cache bandwidth. The bandwidth is computed by the
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number of cache line loaded from the L2 to the L2 data cache and the writebacks from
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the L2 data cache to the L2 cache. The group also outputs total data volume transferred between
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L2 and L1. Note that this bandwidth also includes data transfers due to a write
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allocate load on a store miss in L1 and cache lines transferred it the instruction
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cache.
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