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40 lines
1.5 KiB
Plaintext
40 lines
1.5 KiB
Plaintext
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SHORT TLB miss rate/ratio
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EVENTSET
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FIXC1 ACTUAL_CPU_CLOCK
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FIXC2 MAX_CPU_CLOCK
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PMC0 RETIRED_INSTRUCTIONS
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PMC1 DATA_CACHE_ACCESSES
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PMC2 L1_DTLB_MISS_ANY_L2_HIT
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PMC3 L1_DTLB_MISS_ANY_L2_MISS
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METRICS
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Runtime (RDTSC) [s] time
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Runtime unhalted [s] FIXC1*inverseClock
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Clock [MHz] 1.E-06*(FIXC1/FIXC2)/inverseClock
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CPI FIXC1/PMC0
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L1 DTLB request rate PMC1/PMC0
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L1 DTLB miss rate (PMC2+PMC3)/PMC0
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L1 DTLB miss ratio (PMC2+PMC3)/PMC1
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L2 DTLB request rate (PMC2+PMC3)/PMC0
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L2 DTLB miss rate PMC3/PMC0
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L2 DTLB miss ratio PMC3/(PMC2+PMC3)
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LONG
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Formulas:
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L1 DTLB request rate = DATA_CACHE_ACCESSES / RETIRED_INSTRUCTIONS
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L1 DTLB miss rate = (L1_DTLB_MISS_ANY_L2_HIT+L1_DTLB_MISS_ANY_L2_MISS)/RETIRED_INSTRUCTIONS
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L1 DTLB miss ratio = (L1_DTLB_MISS_ANY_L2_HIT+L1_DTLB_MISS_ANY_L2_MISS)/DATA_CACHE_ACCESSES
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L2 DTLB request rate = (L1_DTLB_MISS_ANY_L2_HIT+L1_DTLB_MISS_ANY_L2_MISS)/RETIRED_INSTRUCTIONS
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L2 DTLB miss rate = L1_DTLB_MISS_ANY_L2_MISS / RETIRED_INSTRUCTIONS
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L2 DTLB miss ratio = L1_DTLB_MISS_ANY_L2_MISS / (L1_DTLB_MISS_ANY_L2_HIT+L1_DTLB_MISS_ANY_L2_MISS)
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-
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L1 DTLB request rate tells you how data intensive your code is
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or how many data accesses you have on average per instruction.
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The DTLB miss rate gives a measure how often a TLB miss occurred
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per instruction. And finally L1 DTLB miss ratio tells you how many
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of your memory references required caused a TLB miss on average.
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NOTE: The L2 metrics are only relevant if L2 DTLB request rate is
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equal to the L1 DTLB miss rate!
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