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https://github.com/ClusterCockpit/cc-metric-collector.git
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36 lines
1.4 KiB
Plaintext
36 lines
1.4 KiB
Plaintext
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SHORT Main memory bandwidth in MBytes/s (experimental)
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EVENTSET
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FIXC1 ACTUAL_CPU_CLOCK
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FIXC2 MAX_CPU_CLOCK
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PMC0 RETIRED_INSTRUCTIONS
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PMC1 CPU_CLOCKS_UNHALTED
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DFC0 DATA_FROM_LOCAL_DRAM_CHANNEL
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DFC1 DATA_TO_LOCAL_DRAM_CHANNEL
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METRICS
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Runtime (RDTSC) [s] time
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Runtime unhalted [s] FIXC1*inverseClock
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Clock [MHz] 1.E-06*(FIXC1/FIXC2)/inverseClock
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CPI PMC1/PMC0
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Memory bandwidth [MBytes/s] 1.0E-06*(DFC0+DFC1)*(4.0/num_numadomains)*64.0/time
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Memory data volume [GBytes] 1.0E-09*(DFC0+DFC1)*(4.0/num_numadomains)*64.0
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LONG
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Formulas:
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Memory bandwidth [MBytes/s] = 4.0E-06*(DATA_FROM_LOCAL_DRAM_CHANNEL+DATA_TO_LOCAL_DRAM_CHANNEL)*(4.0/num_numadomains)*64.0/runtime
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Memory data volume [GBytes] = 4.0E-09*(DATA_FROM_LOCAL_DRAM_CHANNEL+DATA_TO_LOCAL_DRAM_CHANNEL)*(4.0/num_numadomains)*64.0
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-
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Profiling group to measure memory bandwidth drawn by all cores of a socket.
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Since this group is based on Uncore events it is only possible to measure on a
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per socket base.
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The group provides almost accurate results for the total bandwidth
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and data volume.
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The metric formulas contain a correction factor of (4.0/num_numadomains) to
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return the value for all 4 memory controllers in NPS1 mode. This is probably
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a work-around. Requested info from AMD but no answer.
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Be aware that despite the events imply a traffic direction (FROM and TO), the events
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cannot be used to differentiate between read and write traffic. The events will be
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renamed to avoid that confusion in the future.
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