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29 lines
784 B
Plaintext
29 lines
784 B
Plaintext
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SHORT L1 Instruction TLB miss rate/ratio
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EVENTSET
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FIXC0 INSTR_RETIRED_ANY
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FIXC1 CPU_CLK_UNHALTED_CORE
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FIXC2 CPU_CLK_UNHALTED_REF
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PMC0 ITLB_MISSES_CAUSES_A_WALK
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PMC1 ITLB_MISSES_WALK_ACTIVE
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METRICS
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Runtime (RDTSC) [s] time
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Runtime unhalted [s] FIXC1*inverseClock
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Clock [MHz] 1.E-06*(FIXC1/FIXC2)/inverseClock
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CPI FIXC1/FIXC0
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L1 ITLB misses PMC0
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L1 ITLB miss rate PMC0/FIXC0
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L1 ITLB miss duration [Cyc] PMC1/PMC0
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LONG
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Formulas:
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L1 ITLB misses = ITLB_MISSES_CAUSES_A_WALK
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L1 ITLB miss rate = ITLB_MISSES_CAUSES_A_WALK / INSTR_RETIRED_ANY
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L1 ITLB miss duration [Cyc] = ITLB_MISSES_WALK_ACTIVE / ITLB_MISSES_CAUSES_A_WALK
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-
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The ITLB miss rates gives a measure how often a TLB miss occurred
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per instruction. The duration measures the time in cycles how long a walk did take.
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