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38 lines
1.6 KiB
Plaintext
38 lines
1.6 KiB
Plaintext
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SHORT Memory load bandwidth in MBytes/s
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EVENTSET
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FIXC0 INSTR_RETIRED_ANY
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FIXC1 CPU_CLK_UNHALTED_CORE
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FIXC2 CPU_CLK_UNHALTED_REF
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PMC0 LONGEST_LAT_CACHE_MISS
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PMC1 OFFCORE_RESPONSE_1_WB_ANY
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METRICS
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Runtime (RDTSC) [s] time
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Runtime unhalted [s] FIXC1*inverseClock
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Clock [MHz] 1.E-06*(FIXC1/FIXC2)/inverseClock
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CPI FIXC1/FIXC0
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Memory read bandwidth [MBytes/s] 1.0E-06*(PMC0)*64.0/time
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Memory read data volume [GBytes] 1.0E-09*(PMC0)*64.0
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Memory writeback bandwidth [MBytes/s] 1.0E-06*(PMC1)*64.0/time
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Memory writeback data volume [GBytes] 1.0E-09*(PMC1)*64.0
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Memory bandwidth [MBytes/s] 1.0E-06*(PMC0+PMC1)*64.0/time
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Memory data volume [GBytes] 1.0E-09*(PMC0+PMC1)*64.0
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LONG
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Formulas:
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Memory read bandwidth [MBytes/s] = 1.0E-06*(LONGEST_LAT_CACHE_MISS)*64/time
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Memory read data volume [GBytes] = 1.0E-09*(LONGEST_LAT_CACHE_MISS)*64
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Memory writeback bandwidth [MBytes/s] = 1.0E-06*(OFFCORE_RESPONSE_1_WB_ANY)*64/time
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Memory writeback data volume [GBytes] = 1.0E-09*(OFFCORE_RESPONSE_1_WB_ANY)*64
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Memory bandwidth [MBytes/s] = 1.0E-06*(LONGEST_LAT_CACHE_MISS+OFFCORE_RESPONSE_1_WB_ANY)*64/time
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Memory data volume [GBytes] = 1.0E-09*(LONGEST_LAT_CACHE_MISS+OFFCORE_RESPONSE_1_WB_ANY)*64
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-
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Profiling group to measure L2 to MEM load cache bandwidth. The bandwidth is computed by the
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number of cache line allocated in the L2 cache. Since there is no possibility to retrieve
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the evicted cache lines, this group measures only the load cache bandwidth. The
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writeback metrics count only modified cache lines that are written back to go to
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exclusive state
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The group also output totally load and writeback data volume transferred between memory and L2.
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