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35 lines
1.2 KiB
Plaintext
35 lines
1.2 KiB
Plaintext
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SHORT L3 cache miss rate/ratio
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EVENTSET
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FIXC0 INSTR_RETIRED_ANY
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FIXC1 CPU_CLK_UNHALTED_CORE
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FIXC2 CPU_CLK_UNHALTED_REF
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UPMC0 UNC_L3_HITS_ANY
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UPMC1 UNC_L3_MISS_ANY
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METRICS
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Runtime (RDTSC) [s] time
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Runtime unhalted [s] FIXC1*inverseClock
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Clock [MHz] 1.E-06*(FIXC1/FIXC2)/inverseClock
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CPI FIXC1/FIXC0
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L3 request rate (UPMC0+UPMC1)/FIXC0
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L3 miss rate UPMC1/FIXC0
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L3 miss ratio UPMC1/(UPMC0+UPMC1)
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LONG
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Formulas:
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L3 request rate = (UNC_L3_HITS_ANY+UNC_L3_MISS_ANY)/INSTR_RETIRED_ANY
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L3 miss rate = UNC_L3_MISS_ANY/INSTR_RETIRED_ANY
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L3 miss ratio = UNC_L3_MISS_ANY/(UNC_L3_HITS_ANY+UNC_L3_MISS_ANY)
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-
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This group measures the locality of your data accesses with regard to the
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L3 cache. L3 request rate tells you how data intensive your code is
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or how many data accesses you have on average per instruction.
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The L3 miss rate gives a measure how often it was necessary to get
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cache lines from memory. And finally L3 miss ratio tells you how many of your
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memory references required a cache line to be loaded from a higher level.
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While the data cache miss rate might be given by your algorithm you should
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try to get data cache miss ratio as low as possible by increasing your cache reuse.
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