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33 lines
989 B
Plaintext
33 lines
989 B
Plaintext
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SHORT L3 cache bandwidth in MBytes/s
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EVENTSET
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FIXC1 ACTUAL_CPU_CLOCK
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FIXC2 MAX_CPU_CLOCK
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PMC0 RETIRED_INSTRUCTIONS
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PMC1 CPU_CLOCKS_UNHALTED
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CPMC0 L3_ACCESS
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CPMC1 L3_MISS
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METRICS
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Runtime (RDTSC) [s] time
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Runtime unhalted [s] FIXC1*inverseClock
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Clock [MHz] 1.E-06*(FIXC1/FIXC2)/inverseClock
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CPI PMC1/PMC0
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L3 access bandwidth [MBytes/s] 1.0E-06*CPMC0*64.0/time
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L3 access data volume [GBytes] 1.0E-09*CPMC0*64.0
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L3 access rate [%] (CPMC0/PMC0)*100.0
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L3 miss rate [%] (CPMC1/PMC0)*100.0
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L3 miss ratio [%] (CPMC1/CPMC0)*100.0
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LONG
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Formulas:
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L3 access bandwidth [MBytes/s] = 1.0E-06*L3_ACCESS*64.0/time
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L3 access data volume [GBytes] = 1.0E-09*L3_ACCESS*64.0
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L3 access rate [%] = (L3_ACCESS/RETIRED_INSTRUCTIONS)*100
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L3 miss rate [%] = (L3_MISS/RETIRED_INSTRUCTIONS)*100
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L3 miss ratio [%]= (L3_MISS/L3_ACCESS)*100
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-
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Profiling group to measure L3 cache bandwidth. There is no way to measure
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the store traffic between L2 and L3. The only two published L3 events are
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L3_ACCESS and L3_MISS.
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