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35 lines
1.3 KiB
Plaintext
35 lines
1.3 KiB
Plaintext
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SHORT L2 cache miss rate/ratio
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EVENTSET
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FIXC0 INSTR_RETIRED_ANY
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FIXC1 CPU_CLK_UNHALTED_CORE
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FIXC2 CPU_CLK_UNHALTED_REF
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PMC0 MEM_UOPS_RETIRED_L2_HIT_LOADS
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PMC1 MEM_UOPS_RETIRED_L2_MISS_LOADS
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METRICS
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Runtime (RDTSC) [s] time
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Runtime unhalted [s] FIXC1*inverseClock
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Clock [MHz] 1.E-06*(FIXC1/FIXC2)/inverseClock
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CPI FIXC1/FIXC0
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L2 request rate (PMC0+PMC1)/FIXC0
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L2 miss rate PMC1/FIXC0
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L2 miss ratio PMC1/(PMC0+PMC1)
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LONG
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Formulas:
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L2 request rate = (MEM_UOPS_RETIRED_L2_HIT_LOADS+MEM_UOPS_RETIRED_L2_MISS_LOADS)/INSTR_RETIRED_ANY
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L2 miss rate = MEM_UOPS_RETIRED_L2_MISS_LOADS/INSTR_RETIRED_ANY
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L2 miss ratio = MEM_UOPS_RETIRED_L2_MISS_LOADS/(MEM_UOPS_RETIRED_L2_HIT_LOADS+MEM_UOPS_RETIRED_L2_MISS_LOADS)
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-
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This group measures the locality of your data accesses with regard to the
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L2 cache. L2 request rate tells you how data intensive your code is
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or how many data accesses you have on average per instruction.
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The L2 miss rate gives a measure how often it was necessary to get
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cache lines from memory. And finally L2 miss ratio tells you how many of your
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memory references required a cache line to be loaded from a higher level.
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While the data cache miss rate might be given by your algorithm you should
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try to get data cache miss ratio as low as possible by increasing your cache
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reuse.
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