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33 lines
1.2 KiB
Plaintext
33 lines
1.2 KiB
Plaintext
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SHORT L2 cache miss rate/ratio
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EVENTSET
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PMC0 INSTRUCTIONS_RETIRED
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PMC1 L2_REQUESTS_ALL
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PMC2 L2_MISSES_ALL
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PMC3 L2_FILL_ALL
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METRICS
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Runtime (RDTSC) [s] time
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L2 request rate (PMC1+PMC3)/PMC0
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L2 miss rate PMC2/PMC0
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L2 miss ratio PMC2/(PMC1+PMC3)
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LONG
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Formulas:
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L2 request rate = (L2_REQUESTS_ALL+L2_FILL_ALL)/INSTRUCTIONS_RETIRED
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L2 miss rate = L2_MISSES_ALL/INSTRUCTIONS_RETIRED
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L2 miss ratio = L2_MISSES_ALL/(L2_REQUESTS_ALL+L2_FILL_ALL)
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-
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This group measures the locality of your data accesses with regard to the
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L2 cache. L2 request rate tells you how data intensive your code is
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or how many data accesses you have on average per instruction.
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The L2 miss rate gives a measure how often it was necessary to get
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cache lines from memory. And finally L2 miss ratio tells you how many of your
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memory references required a cache line to be loaded from a higher level.
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While the# data cache miss rate might be given by your algorithm you should
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try to get data cache miss ratio as low as possible by increasing your cache reuse.
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This group was taken from the whitepaper -Basic Performance Measurements for AMD Athlon 64,
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AMD Opteron and AMD Phenom Processors- from Paul J. Drongowski.
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