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36 lines
1.4 KiB
Plaintext
36 lines
1.4 KiB
Plaintext
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SHORT L3 cache miss rate/ratio
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EVENTSET
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PMC0 RETIRED_INSTRUCTIONS
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UPMC0 UNC_READ_REQ_TO_L3_ALL
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UPMC1 UNC_L3_CACHE_MISS_ALL
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UPMC2 UNC_L3_LATENCY_CYCLE_COUNT
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UPMC3 UNC_L3_LATENCY_REQUEST_COUNT
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METRICS
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Runtime (RDTSC) [s] time
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L3 request rate UPMC0/PMC0
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L3 miss rate UPMC1/PMC0
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L3 miss ratio UPMC1/UPMC0
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L3 average access latency [cycles] UPMC2/UPMC3
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LONG
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Formulas:
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L3 request rate = UNC_READ_REQ_TO_L3_ALL/INSTRUCTIONS_RETIRED
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L3 miss rate = UNC_L3_CACHE_MISS_ALL/INSTRUCTIONS_RETIRED
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L3 miss ratio = UNC_L3_CACHE_MISS_ALL/UNC_READ_REQ_TO_L3_ALL
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L3 average access latency = UNC_L3_LATENCY_CYCLE_COUNT/UNC_L3_LATENCY_REQUEST_COUNT
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-
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This group measures the locality of your data accesses with regard to the L3
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Cache. L3 request rate tells you how data intensive your code is or how many
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data accesses you have on average per instruction. The L3 miss rate gives a
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measure how often it was necessary to get cache lines from memory. And finally
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L3 miss ratio tells you how many of your memory references required a cache line
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to be loaded from a higher level. While the# data cache miss rate might be
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given by your algorithm you should try to get data cache miss ratio as low as
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possible by increasing your cache reuse. This group was inspired from the
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whitepaper - Basic Performance Measurements for AMD Athlon 64, AMD Opteron and
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AMD Phenom Processors - from Paul J. Drongowski.
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