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28 lines
785 B
Plaintext
28 lines
785 B
Plaintext
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SHORT L2 data TLB miss rate/ratio
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EVENTSET
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FIXC0 INSTR_RETIRED_ANY
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FIXC1 CPU_CLK_UNHALTED_CORE
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FIXC2 CPU_CLK_UNHALTED_REF
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PMC0 PAGE_WALKS_D_SIDE_COUNT
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PMC1 PAGE_WALKS_D_SIDE_CYCLES
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METRICS
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Runtime (RDTSC) [s] time
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Runtime unhalted [s] FIXC1*inverseClock
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Clock [MHz] 1.E-06*(FIXC1/FIXC2)/inverseClock
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CPI FIXC1/FIXC0
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L1 DTLB misses PMC0
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L1 DTLB miss rate PMC0/FIXC0
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L1 DTLB miss duration [Cyc] PMC1/PMC0
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LONG
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Formulas:
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L1 DTLB misses = PAGE_WALKS_D_SIDE_COUNT
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L1 DTLB miss rate = PAGE_WALKS_D_SIDE_COUNT / INSTR_RETIRED_ANY
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L1 DTLB miss duration [Cyc] = PAGE_WALKS_D_SIDE_CYCLES / PAGE_WALKS_D_SIDE_COUNT
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-
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The DTLB load and store miss rates gives a measure how often a TLB miss occurred
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per instruction. The duration measures the time in cycles how long a walk did take.
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