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36 lines
1.2 KiB
Plaintext
36 lines
1.2 KiB
Plaintext
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SHORT L2 data TLB miss rate/ratio
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EVENTSET
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FIXC0 INSTR_RETIRED_ANY
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FIXC1 CPU_CLK_UNHALTED_CORE
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FIXC2 CPU_CLK_UNHALTED_REF
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PMC0 DTLB_LOAD_MISSES_CAUSES_A_WALK
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PMC1 DTLB_STORE_MISSES_CAUSES_A_WALK
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PMC2 DTLB_LOAD_MISSES_WALK_DURATION
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PMC3 DTLB_STORE_MISSES_WALK_DURATION
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METRICS
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Runtime (RDTSC) [s] time
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Runtime unhalted [s] FIXC1*inverseClock
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Clock [MHz] 1.E-06*(FIXC1/FIXC2)/inverseClock
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CPI FIXC1/FIXC0
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L1 DTLB load misses PMC0
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L1 DTLB load miss rate PMC0/FIXC0
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L1 DTLB load miss duration PMC2
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L1 DTLB store misses PMC1
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L1 DTLB store miss rate PMC1/FIXC0
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L1 DTLB store miss duration PMC3
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LONG
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Formulas:
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L1 DTLB load misses = DTLB_LOAD_MISSES_CAUSES_A_WALK
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L1 DTLB load miss rate = DTLB_LOAD_MISSES_CAUSES_A_WALK / INSTR_RETIRED_ANY
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L1 DTLB load miss duration = DTLB_LOAD_MISSES_WALK_DURATION
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L1 DTLB store misses = DTLB_STORE_MISSES_CAUSES_A_WALK
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L1 DTLB store miss rate = DTLB_STORE_MISSES_CAUSES_A_WALK / INSTR_RETIRED_ANY
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L1 DTLB store miss duration = DTLB_STORE_MISSES_WALK_DURATION
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-
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The DTLB load and store miss rates gives a measure how often a TLB miss occurred
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per instruction. The duration measures the time in cycles how long a walk did take.
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