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49 lines
1.9 KiB
Plaintext
49 lines
1.9 KiB
Plaintext
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SHORT Top down cycle allocation
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EVENTSET
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FIXC0 INSTR_RETIRED_ANY
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FIXC1 CPU_CLK_UNHALTED_CORE
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FIXC2 CPU_CLK_UNHALTED_REF
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PMC0 UOPS_ISSUED_ANY
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PMC1 UOPS_RETIRED_RETIRE_SLOTS
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PMC2 IDQ_UOPS_NOT_DELIVERED_CORE
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PMC3 INT_MISC_RECOVERY_CYCLES
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METRICS
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Runtime (RDTSC) [s] time
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Runtime unhalted [s] FIXC1*inverseClock
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Clock [MHz] 1.E-06*(FIXC1/FIXC2)/inverseClock
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CPI FIXC1/FIXC0
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IPC FIXC0/FIXC1
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Total Slots 4*FIXC1
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Slots Retired PMC1
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Fetch Bubbles PMC2
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Recovery Bubbles 4*PMC3
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Front End [%] PMC2/(4*FIXC1)*100
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Speculation [%] (PMC0-PMC1+(4*PMC3))/(4*FIXC1)*100
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Retiring [%] PMC1/(4*FIXC1)*100
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Back End [%] (1-((PMC2+PMC0+(4*PMC3))/(4*FIXC1)))*100
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LONG
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Formulas:
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Total Slots = 4*CPU_CLK_UNHALTED_CORE
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Slots Retired = UOPS_RETIRED_RETIRE_SLOTS
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Fetch Bubbles = IDQ_UOPS_NOT_DELIVERED_CORE
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Recovery Bubbles = 4*INT_MISC_RECOVERY_CYCLES
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Front End [%] = IDQ_UOPS_NOT_DELIVERED_CORE/(4*CPU_CLK_UNHALTED_CORE)*100
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Speculation [%] = (UOPS_ISSUED_ANY-UOPS_RETIRED_RETIRE_SLOTS+(4*INT_MISC_RECOVERY_CYCLES))/(4*CPU_CLK_UNHALTED_CORE)*100
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Retiring [%] = UOPS_RETIRED_RETIRE_SLOTS/(4*CPU_CLK_UNHALTED_CORE)*100
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Back End [%] = (1-((IDQ_UOPS_NOT_DELIVERED_CORE+UOPS_ISSUED_ANY+(4*INT_MISC_RECOVERY_CYCLES))/(4*CPU_CLK_UNHALTED_CORE)))*100
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--
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This performance group measures cycles to determine percentage of time spent in
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front end, back end, retiring and speculation. These metrics are published and
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verified by Intel. Further information:
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Webpage describing Top-Down Method and its usage in Intel vTune:
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https://software.intel.com/en-us/vtune-amplifier-help-tuning-applications-using-a-top-down-microarchitecture-analysis-method
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Paper by Yasin Ahmad:
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https://sites.google.com/site/analysismethods/yasin-pubs/TopDown-Yasin-ISPASS14.pdf?attredirects=0
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Slides by Yasin Ahmad:
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http://www.cs.technion.ac.il/~erangi/TMA_using_Linux_perf__Ahmad_Yasin.pdf
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The performance group was originally published here:
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http://perf.mvermeulen.com/2018/04/14/top-down-performance-counter-analysis-part-1-likwid/
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