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41 lines
1.7 KiB
Plaintext
41 lines
1.7 KiB
Plaintext
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SHORT L2 cache bandwidth in MBytes/s
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EVENTSET
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PMC0 INST_RETIRED
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PMC1 CPU_CYCLES
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PMC2 L1D_CACHE_REFILL
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PMC3 L1D_CACHE_WB
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PMC4 L1I_CACHE_REFILL
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METRICS
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Runtime (RDTSC) [s] time
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CPI PMC1/PMC0
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L1D<-L2 load bandwidth [MBytes/s] 1.0E-06*(PMC2)*256.0/time
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L1D<-L2 load data volume [GBytes] 1.0E-09*(PMC2)*256.0
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L1D->L2 evict bandwidth [MBytes/s] 1.0E-06*PMC3*256.0/time
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L1D->L2 evict data volume [GBytes] 1.0E-09*PMC3*256.0
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L1I<-L2 load bandwidth [MBytes/s] 1.0E-06*PMC4*256.0/time
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L1I<-L2 load data volume [GBytes] 1.0E-09*PMC4*256.0
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L1<->L2 bandwidth [MBytes/s] 1.0E-06*(PMC2+PMC3+PMC4)*256.0/time
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L1<->L2 data volume [GBytes] 1.0E-09*(PMC2+PMC3+PMC4)*256.0
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LONG
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Formulas:
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CPI = CPU_CYCLES/INST_RETIRED
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L1D<-L2 load bandwidth [MBytes/s] = 1.0E-06*L1D_CACHE_REFILL*256.0/time
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L1D<-L2 load data volume [GBytes] = 1.0E-09*L1D_CACHE_REFILL*256.0
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L1D->L2 evict bandwidth [MBytes/s] = 1.0E-06*L1D_CACHE_WB*256.0/time
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L1D->L2 evict data volume [GBytes] = 1.0E-09*L1D_CACHE_WB*256.0
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L1I<-L2 load bandwidth [MBytes/s] = 1.0E-06*L1I_CACHE_REFILL*256.0/time
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L1I<-L2 load data volume [GBytes] = 1.0E-09*L1I_CACHE_REFILL*256.0
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L1<->L2 bandwidth [MBytes/s] = 1.0E-06*(L1D_CACHE_REFILL+L1D_CACHE_WB+L1I_CACHE_REFILL)*256.0/time
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L1<->L2 data volume [GBytes] = 1.0E-09*(L1D_CACHE_REFILL+L1D_CACHE_WB+L1I_CACHE_REFILL)*256.0
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-
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Profiling group to measure L2 cache bandwidth. The bandwidth is computed by the
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number of cacheline loaded from the L2 to the L1 data cache and the writebacks from
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the L1 data cache to the L2 cache. The group also outputs total data volume transfered between
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L2 and L1. Note that this bandwidth also includes data transfers due to a write
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allocate load on a store miss in L1 and cachelines transfered in the L1 instruction
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cache.
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