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27 lines
645 B
Plaintext
27 lines
645 B
Plaintext
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SHORT Data cache miss rate/ratio
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EVENTSET
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FIXC0 INSTR_RETIRED_ANY
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FIXC1 CPU_CLK_UNHALTED_CORE
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FIXC2 CPU_CLK_UNHALTED_REF
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PMC0 L1D_REPL
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METRICS
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Runtime (RDTSC) [s] time
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Runtime unhalted [s] FIXC1*inverseClock
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Clock [MHz] 1.E-06*(FIXC1/FIXC2)/inverseClock
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CPI FIXC1/FIXC0
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data cache misses PMC0
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data cache miss rate PMC0/FIXC0
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LONG
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Formulas:
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data cache misses = L1D_REPL
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data cache miss rate = L1D_REPL / INSTR_RETIRED_ANY
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-
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This group measures the locality of your data accesses with regard to the
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L1 cache.
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The data cache miss rate gives a measure how often it was necessary to get
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cache lines from higher levels of the memory hierarchy.
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