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38 lines
1000 B
Plaintext
38 lines
1000 B
Plaintext
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SHORT L1 Data TLB miss rate/ratio
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EVENTSET
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PMC0 PM_DTLB_MISS_16G
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PMC1 PM_DTLB_MISS_4K
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PMC2 PM_DTLB_MISS_64K
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PMC3 PM_DTLB_MISS_16M
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PMC4 PM_RUN_INST_CMPL
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PMC5 PM_RUN_CYC
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METRICS
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Runtime (RDTSC) [s] time
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CPI PMC5/PMC4
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L1 DTLB 4K misses PMC1
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L1 DTLB 4K miss rate PMC1/PMC4
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L1 DTLB 64K misses PMC2
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L1 DTLB 64K miss rate PMC2/PMC4
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L1 DTLB 16M misses PMC3
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L1 DTLB 16M miss rate PMC3/PMC4
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L1 DTLB 16G misses PMC0
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L1 DTLB 16G miss rate PMC0/PMC4
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LONG
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Formulas:
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CPI = PM_RUN_CYC / PM_RUN_INST_CMPL
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L1 DTLB 4K misses = PM_DTLB_MISS_4K
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L1 DTLB 4K miss rate = PM_DTLB_MISS_4K/PM_RUN_INST_CMPL
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L1 DTLB 64K misses = PM_DTLB_MISS_64K
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L1 DTLB 64K miss rate = PM_DTLB_MISS_64K/PM_RUN_INST_CMPL
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L1 DTLB 16M misses = PM_DTLB_MISS_16M
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L1 DTLB 16M miss rate = PM_DTLB_MISS_16M/PM_RUN_INST_CMPL
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L1 DTLB 16G misses = PM_DTLB_MISS_16G
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L1 DTLB 16G miss rate = PM_DTLB_MISS_16G/PM_RUN_INST_CMPL
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--
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The DTLB load and store miss rates gives a measure how often a TLB miss occured
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per instruction.
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