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35 lines
1.5 KiB
Plaintext
35 lines
1.5 KiB
Plaintext
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SHORT Double Precision MFLOP/s
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EVENTSET
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FIXC0 INSTR_RETIRED_ANY
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FIXC1 CPU_CLK_UNHALTED_CORE
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FIXC2 CPU_CLK_UNHALTED_REF
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PMC0 UOPS_RETIRED_SCALAR_SIMD
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PMC1 UOPS_RETIRED_PACKED_SIMD
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METRICS
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Runtime (RDTSC) [s] time
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Runtime unhalted [s] FIXC1*inverseClock
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Clock [MHz] 1.E-06*(FIXC1/FIXC2)/inverseClock
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CPI FIXC1/FIXC0
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DP [MFLOP/s] (SSE assumed) 1.0E-06*((PMC1*2.0)+PMC0)/time
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DP [MFLOP/s] (AVX assumed) 1.0E-06*((PMC1*4.0)+PMC0)/time
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DP [MFLOP/s] (AVX512 assumed) 1.0E-06*((PMC1*8.0)+PMC0)/time
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Packed [MUOPS/s] 1.0E-06*(PMC1)/time
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Scalar [MUOPS/s] 1.0E-06*PMC0/time
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LONG
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Formulas:
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DP [MFLOP/s] (SSE assumed) = 1.0E-06*(UOPS_RETIRED_PACKED_SIMD*2+UOPS_RETIRED_SCALAR_SIMD)/runtime
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DP [MFLOP/s] (AVX assumed) = 1.0E-06*(UOPS_RETIRED_PACKED_SIMD*4+UOPS_RETIRED_SCALAR_SIMD)/runtime
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DP [MFLOP/s] (AVX512 assumed) = 1.0E-06*(UOPS_RETIRED_PACKED_SIMD*8+UOPS_RETIRED_SCALAR_SIMD)/runtime
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Packed [MUOPS/s] = 1.0E-06*(UOPS_RETIRED_PACKED_SIMD)/runtime
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Scalar [MUOPS/s] = 1.0E-06*UOPS_RETIRED_SCALAR_SIMD/runtime
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-
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AVX/SSE scalar and packed double precision FLOP rates. The Xeon Phi (Knights Landing) provides
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no possibility to differentiate between double and single precision FLOP/s. Therefore, we only
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assume that the printed [MFLOP/s] value is for double-precision code. Moreover, there is no way
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to distinguish between SSE, AVX or AVX512 packed SIMD operations. Therefore, this group prints
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out the [MFLOP/s] for different SIMD techniques.
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WARNING: The events also count for integer arithmetics
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