SHORT L2 cache miss rate/ratio

EVENTSET
PMC0  PM_L2_ST_MISS
PMC1  PM_L2_LD_MISS
PMC2  PM_L2_LD_DISP
PMC3  PM_L2_ST_DISP
PMC4  PM_RUN_INST_CMPL
PMC5  PM_RUN_CYC


METRICS
Runtime (RDTSC) [s] time
CPI  PMC5/PMC4
L2 request rate = (PMC2+PMC3)/PMC4
L2 miss rate = (PMC0+PMC1)/PMC4
L2 miss ratio = (PMC0+PMC1)/(PMC2+PMC3)

LONG
Formulas:
L2 request rate = (PM_L2_LD_DISP+PM_L2_ST_DISP)/PM_RUN_INST_CMPL
L2 miss rate = (PM_L2_LD_MISS+PM_L2_ST_MISS)/PM_RUN_INST_CMPL
L2 miss ratio = (PM_L2_LD_MISS+PM_L2_ST_MISS)/(PM_L2_LD_DISP+PM_L2_ST_DISP)
L2 load request rate = PM_L2_LD_DISP/PM_RUN_INST_CMPL
L2 store request rate = PM_L2_ST_DISP/PM_RUN_INST_CMPL
L2 load miss rate = PM_L2_LD_MISS/PM_RUN_INST_CMPL
L2 store miss rate = PM_L2_ST_DISP/PM_RUN_INST_CMPL
L2 load miss ratio = PM_L2_LD_MISS/(PM_L2_LD_DISP+PM_L2_ST_DISP)
L2 store miss ratio = PM_L2_ST_MISS/(PM_L2_LD_DISP+PM_L2_ST_DISP)
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This group measures the locality of your data accesses with regard to the
L2 Cache. L2 request rate tells you how data intensive your code is
or how many Data accesses you have in average per instruction.
The L2 miss rate gives a measure how often it was necessary to get
cachelines from memory. And finally L2 miss ratio tells you how many of your
memory references required a cacheline to be loaded from a higher level.
While the Data cache miss rate might be given by your algorithm you should
try to get Data cache miss ratio as low as possible by increasing your cache reuse.


