SHORT  L2 data TLB miss rate/ratio

EVENTSET
FIXC0 INSTR_RETIRED_ANY
FIXC1 CPU_CLK_UNHALTED_CORE
FIXC2 CPU_CLK_UNHALTED_REF
PMC0  PAGE_WALKS_D_SIDE_COUNT
PMC1  PAGE_WALKS_D_SIDE_CYCLES

METRICS
Runtime (RDTSC) [s] time
Runtime unhalted [s] FIXC1*inverseClock
Clock [MHz]  1.E-06*(FIXC1/FIXC2)/inverseClock
CPI  FIXC1/FIXC0
L1 DTLB misses     PMC0
L1 DTLB miss rate  PMC0/FIXC0
L1 DTLB miss duration [Cyc] PMC1/PMC0

LONG
Formulas:
L1 DTLB misses = PAGE_WALKS_D_SIDE_COUNT
L1 DTLB miss rate = PAGE_WALKS_D_SIDE_COUNT / INSTR_RETIRED_ANY
L1 DTLB miss duration [Cyc] = PAGE_WALKS_D_SIDE_CYCLES / PAGE_WALKS_D_SIDE_COUNT
-
The DTLB load and store miss rates gives a measure how often a TLB miss occurred
per instruction. The duration measures the time in cycles how long a walk did take.

