SHORT  L1 Data TLB miss rate/ratio

EVENTSET
PMC0  PM_DTLB_MISS_16G
PMC1  PM_DTLB_MISS_4K
PMC2  PM_DTLB_MISS_64K
PMC3  PM_DTLB_MISS_16M
PMC4  PM_RUN_INST_CMPL
PMC5  PM_RUN_CYC

METRICS
Runtime (RDTSC) [s] time
CPI  PMC5/PMC4
L1 DTLB 4K misses     PMC1
L1 DTLB 4K miss rate  PMC1/PMC4
L1 DTLB 64K misses     PMC2
L1 DTLB 64K miss rate  PMC2/PMC4
L1 DTLB 16M misses     PMC3
L1 DTLB 16M miss rate  PMC3/PMC4
L1 DTLB 16G misses     PMC0
L1 DTLB 16G miss rate  PMC0/PMC4

LONG
Formulas:
CPI = PM_RUN_CYC / PM_RUN_INST_CMPL
L1 DTLB 4K misses = PM_DTLB_MISS_4K
L1 DTLB 4K miss rate = PM_DTLB_MISS_4K/PM_RUN_INST_CMPL
L1 DTLB 64K misses = PM_DTLB_MISS_64K
L1 DTLB 64K miss rate = PM_DTLB_MISS_64K/PM_RUN_INST_CMPL
L1 DTLB 16M misses = PM_DTLB_MISS_16M
L1 DTLB 16M miss rate = PM_DTLB_MISS_16M/PM_RUN_INST_CMPL
L1 DTLB 16G misses = PM_DTLB_MISS_16G
L1 DTLB 16G miss rate = PM_DTLB_MISS_16G/PM_RUN_INST_CMPL
--
The DTLB load and store miss rates gives a measure how often a TLB miss occured
per instruction.

